When two CCD cells are placed very close together (spacing~μm), if a positive bias voltage is simultaneously applied to two adjacent gates, the potential wells under these two gates merge into one, as shown below.


When the bias of the left cell changes to0under the influence of the electric field, the merged potential well becomes a single well, and the overall effect is that the charge packet moves to the right cell, as shown below.


Three-phase design: each pixel has3gates, and the gates at corresponding positions in each row of pixels are connected together, as shown below. During exposure, only one gate is biased. After exposure, a timing circuit drives the gates so that the charge packets of one row of pixels are simultaneously shifted down by one row. The charge packets of the bottom row of pixels are shifted into the horizontal shift register. The horizontal shift register moves horizontally, shifting out, amplifying, and digitizing the charge packets of each pixel one by one, and sending them to the computer for processing. The horizontal shift register is also aCCDcoupled device, except that the register in the middle has two shift-in ports and has some other functions.


The following is the timing and shifting results of the three-phase coupling structure


Electrode voltageState
StepΦ1Φ2Φ3
1V00During exposure, the P1 electrode is biased, forming a potential well under the gate to collect photoelectrons and form a charge packet
2VV0After exposure, P2 is biased, and the potential wells under P1 and P2 merge into one, and the charge packet is shared
30V0When the bias voltage on P1 is removed, the charge packet moves under the P2 electrode.
40VVThe P2 and P3 potential wells merge into one
500VThe charge packet moves under the P3 electrode
6V0VThe P3 potential well of the previous pixel merges with the P1 potential well of the current pixel, and the charge packet is shared; the charge packet of the current pixel is under the P3 gate and is shared with the P1 potential well of the next pixel
7V00When the bias on P3 is removed, the charge packet of the previous row of pixels moves to the current pixel, and the charge packet of the current pixel moves to the next row of pixels.
Continue the above steps until the charge packets of all rows are shifted into the horizontal shift register, and then moved horizontally to the amplifier until all pixel charge packets are read out.


An animation on Wikipedia vividly illustrates the charge packet transfer process


Of course, there are other designs for the coupling transfer structure, such as two-phase and four-phase designs.


The above content was compiled and collected by Jerry Huang of our company, for the purpose of knowledge sharing and mutual learning only, and may not be reproduced without permission.